| Features | OrCAD X Standard | OrCAD X Professional | ALLEGRO X Artist | ALLEGRO X Designer | ALLEGRO X Designer Plus | ALLEGRO X Venture |
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| Floating Networked License |
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| 12 Months Maintenance Support Included In Purchase Price |
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| SCHEMATIC ENTRY + DATA MANAGEMENT | ||||||
| Flexible Window layout |
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| Graphical, flat and hierarchical page editor and Picture block hierarchy |
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| OrCAD PSpice AD Basic - Restricted Capacity - see PSpice Matrix below |
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| Net Groups - Complex bus definition |
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| AutoWire |
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| 44,000 Schematic symbols |
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| Coloured Components / nets |
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| Tcl TK scripting support |
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| Online design rule check including custom DRC capability and Waive DRC |
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| Forward and back-annotation of properties / pin-and-gate swaps |
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| Schematic Part and Library editor |
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| Cross-probing and cross-placing |
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| FPGA design-in / pin import & export |
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| Multiple PCB netlist interfaces - New Design Sync for Cadence Flow |
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| UltraLibrarian, Samacsys and SnapMagic (Symbol, Footprint 3d Step Model) |
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| Property editor for pins, components, nets |
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| OrCAD SigXplorer SI Analysis |
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| Intelligent PDF creation |
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| Advanced Annotation |
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| Design Compare (detail and Graphical) |
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| Default Demo designs |
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| Extended Preferences |
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| Export ISCF (Intel Schematic Connectivity Format) |
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| Export / Import XML |
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| Altium Importer Schematic (PCB also available) |
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| Eagle Importer Schematic (PCB also available) |
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| Constraint Manager |
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| Ability to create. manage part database schema and libraries in cloud |
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| Manage Virtual team and collaboration workspaces |
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| Ability to share and work collaboratively for libraries and design |
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| OrCAD X Cloud Services |
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| LiveBOM using Datalynq and Sourcengine |
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| Component Information System |
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| Windows ODBC compatible format |
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| Interface to relational database and management systems |
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| Database query for part selection and parametric properties |
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| Schematic and BOM Variants Manager (Parts not Fitted and more) |
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| Component Information Portal (CIP), Access to Mouser, Digikey, Future, Farnell |
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| DE-HDL / System Capture |
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| PCB EDITOR | ||||||
| Markup for design reviews |
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| Spacing, Same net, Netclass and Class to Class rules |
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| Physical Constraint Rules |
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| 3D DRC Rules(Component to Component, Board, Rigid-flex) |
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| DesignTrue DFM Wizard |
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| Design for Test Checks (Core) |
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| Design for Test Checks (Advanced) |
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| Design For Assembly Checks (Core) |
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| Design For Assembly Checks (Advanced) |
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| Design For Fabrication Checks (Core) |
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| Design For Fabrication Checks (Advanced) |
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| Component Lead Editor |
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| Import File Manager |
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| DFM Pad Entry / Exit Rules |
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| Dynamic pad suppression / Unused Pad removal |
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| Cross Section Editor |
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| Padstack Editor IPC2581 Compliant |
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| Application Mode (General, Etch, Placement) |
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| Application Mode (shape) |
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| Full Skill Support |
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| Customisable Visibility Pane |
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| Dynamic Shape Pin Connection By Layer (Global/Shape/Pin/Layer) |
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| Dynamic Cross Hatch Shapes |
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| Dynamic Shapes (dynamic copper pours) Plow and Heal |
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| Move with autoroute adjust (Slide) |
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| Multiple placement options, manual, quickplace, auto and room |
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| Alignment x and y for components and modules |
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| Dynamic rat suppression |
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| Fan-out generators |
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| Interactive Routing using Working Layer (layer selection popup) |
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| Group route Bus Route and via patterns |
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| Line Fattening |
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| Differential Pair Static Phase Control rules |
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| Differential Pairs Physical rules and routing |
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| Intra Differential Pairs Spacing Rules |
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| Via Voiding Differential Pairs |
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| Blind Buried Single Click multiple via instantiation |
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| Push, Shove and Hug interactive editing |
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| Curve Routing |
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| Snake Routing for Hex pattern ICs |
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| Auto Finish (Route Completion Tool) |
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| Scribble Sketch Routing |
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| Route cleanup, optimization (Glossing) |
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| Embedded net names |
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| Split View |
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| Through Board Transparency (OpenGL) |
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| Flip Board |
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| Excellon NC Drill File export |
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| Gerber 274X, 274D artwork Output |
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| IPC2581 Import / Export |
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| Import Export Mentor ODB++ |
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| Impedance Calculator |
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| Interactive / Automatic Silkscreen generation |
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| Import Altium PCB (schematic also available) |
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| Import EAGLE PCB (schematic also available) |
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| Import PADS & PCAD |
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| Import IFF RF Shapes |
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| Import Export DXF |
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| Import Export IDF |
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| Export Intelligent PDF |
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| MCAD/ECAD Incremental data exchange (IDX. MCADX, AutoDESK Pluggin) |
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| 3D/2D Crossprobing |
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| STEP 3D Clash Detect |
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| STEP 3D viewer for selected item or complete PCB |
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| STEP 3D Canvas Controls |
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| STEP 3D Import Export |
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| STEP 3D Canvas Highlight Selections |
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| Manual Design For Test (DFT) / Test Prep |
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| Associative Dimensioning |
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| Route Nets by Pick, 6- Metal Layers limit, no Pin Limit |
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| Route Automatic, 6- Signal Layers, no layer or Pin Limit |
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| Net Scheduling, T-Point rules (pin to T-point), T-Point definition |
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| Constraint Regions, region based rules (Rigid-Flex; BGA regions) |
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| Propagation delay rules (Relative) for nets or groups |
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| Propagation delay rules (Min/Max) for nets or groups |
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| Total Etch Length - Max/Min Length |
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| Extended (X)net rules |
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| Layer set rules |
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| Pin Pair rules |
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| Delay Tuning |
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| Dynamic Heads-up Display for critical rules |
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| Hug Contour routing (Flex) |
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| Segment over void detection |
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| Spread lines between voids |
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| Shape based curve fillet support, tapered traces |
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| Placement replication, template based design reuse |
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| Via array / Shielding - Shape and Trace based |
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| Rigid Flexi Zone Management |
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| Dynamic Zone Placement |
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| Inter Layer Checks for Rigid Flexi |
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| 3D Bending |
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| High Speed Analysis Impedance Workflow |
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| High Speed Analysis Coupling Workflow |
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| Placement Vision |
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| Route Vision |
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| Differential Pair Dynamic Phase Control rules |
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| Package Pin Delay (for die-2-die delay) rules |
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| Z-Axis delay feedback |
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| Backdrilling |
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| Automatic Design For Test (DFT) / Test Prep |
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| Panelization |
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| Batchplot |
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| Coil Designer |
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| Custom Variables |
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| Polar Grid |
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| Automatic Post Processing |
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| Z-DRC |
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| Match / Max Via Count rules |
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| Offset Routing |
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| Design planning - Create hierarchical Bundles |
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| Design planning - Create, Edit Flows, Assign Flows to Layers |
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| Dynamic Shape based curve fillet support, tapered traces |
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| RF Traces |
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| Design Link (Link Constraints from multiple boards) |
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| Design For Assembly - Placement Control |
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| Electrical Constraint Set (ECSet) Reuse |
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| Chip on Board |
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| Allegro Constraint Compiler |
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| High Speed Return Path DRC |
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| Timing Environment - Auto Delay Tune (AiDT), Auto Phase Tune (AiPT), Remove Tuning |
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| Tabbed Routing |
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| Electrical Constraint rule set (ECSets) / Topology Apply |
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| Electrical rules (Reflection, Timing, Crosstalk) |
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| Advanced Constraints (formulas, relational) |
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| Fibre Weave Effect Zig Zag Auto Interactive |
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| Static Phase Via Transition DRC |
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| Single net Return Paths Vias |
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| Differential Pair Return Path Vias |
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| High Speed Via Structures |
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| High Speed Inductance Via Structures |
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| Creepage and Clearance Vision |
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| Return Path DRC Vision |
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| Impedance DRC Vision |
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| Topology Extraction Workflow |
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| Interconnect Model Extraction Workflow |
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| Crosstalk Workflow (Load results only) |
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| Return Path Workflow (Load results only) |
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| Power Inductance Workflow (Load results only) |
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| IR Drop Analysis Workflow (Load results only) |
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| Reflection Analysis Workflow (Load results only) |
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| Thermal Workflow (Load results only) |
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| Constraint Manager: HDI rule set |
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| Micro-via and associated spacing, stacking and via-in-pad rules |
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| Constraint driven HDI design flow |
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| HDI micro-via stack editing |
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| Creepage and Clearance Rules |
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| Manufacturing rule support for embedding components |
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| Embed components on inner layers |
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| Support for Cavities on inner layers |
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| Support for Vertically placed components on inner layers |
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| Soldermask for embedded components |
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| Support for copy and swap embedded components |
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| Dual Side Contact Embedded Components |
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| Custom DRC rules using Ravel (Run capability) |
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| Custom DRC rules using Ravel (Developer) |
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| Generic GPU Acceleration (Nvidia, AMD, Intel) |
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| Power Delivery Generator |
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| Design Planning - Plan Spatial Feasibility analysis & feedback |
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| Design Planning - Generate Topological Plan |
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| Design Planning - Convert Topological plan to traces (CLINES) |
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| Auto Interactive Break-out (AiBT) |
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| Auto Connect (Breakout, Connect, Compress, Spread, Nudge, Push) |
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| Symphony 2 user Team Design using OrCAD X Presto (cloud based) |
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| Symphony Team Design Option, one board with multiple designers in real time |
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| Parameterized RF etch elements |
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| Asymmetrical Clearances |
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| RF Etch elements editing |
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| Bi-Directional interface with Agilent ADS |
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| ADS schematics Import Agilent into DE-HDL |
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| Layout-driven RF design creation |
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| Flexible Shape Editor |
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| SIGNAL INTEGRITY | ||||||
| Pre- & Post-route signal integrity analysis |
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| Graphical topology definition and exploration |
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| Interactive waveform viewer |
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| IBIS 5.0 support |
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| Lossy transmission lines |
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| Coupled (3 net) simulation Pre-Route |
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| Differential pair exploration and simulation |
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| PSpice SIMULATION | ||||||
| Simulation capacity: 250 Nodes, 250 devices, 1M Transient, 10K AC / DC Sweep, limits |
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| Analog Devices: all except BSIM 3.3, BSIM4, Magnetic Core, IGBT, Tlines, DMI |
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| Analog behavioural modelling |
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| Digital Devices: All |
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| Learning PSpice Free Templates |
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| Bias Point, DC sweep, AC sweep and Transient analysis (with Temperature) |
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| Bias point voltages, currents and power display in Schematic |
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| Modelling Application in Capture |
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| Parametric Sweep |
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| Monte Carlo / Worst Case |
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| Check Point restart |
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| Auto Convergence, Advanced Convergence and Speed Mode |
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| Interactive waveform viewer and analyzer |
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| Waveform: FFT |
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| Advanced tools: FRA, Core loss |
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| PSpice video: Example Design Simple Circuit 1 |
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| PSpice video: Example Design Simple Circuit 2 |
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| PSpice video: Example Design Simple Circuit 3 |
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| PSpPice video: Example Design Simple Circuit 4 |
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| PSpice video: Example Design Simple Circuit 5 |
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| PSpice video: Example Design Simple Circuit 6 |
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| PSpice video: Example Design Simple Circuit 7 |
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| Performance Analysis |
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| Model Editor, Stimulus Editor, Magnetic Parts Editor |
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| Advanced Analysis: Smoke (Stress) |
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| Advanced Analysis: Optimiser, Sensitivity, Monte Carlo |
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| Advanced Analysis: Parametric Plotter |
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| PSpice - MATLAB Interface: Co-Simulation, Visualisation, Functions |
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| Analog Devices: All |
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| Simulation capacity: unlimited |
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